REFLECTIVE MEMORY AND DISTRIBUTED SHARED MEMORY ARCHITECTURES FOR OLTP
Coordinator: Ilya Gertner
ARC 1 Reflective Memory and Distributed Shared Memory Architectures for OLTP I
€ Introduction to the Minitrack, I. Gertner
€ A Survey of Distributed Shared Memory Systems, J. Protic, M. Tomasevic, and V. Milutinovic
€ Reflective-Memory Multiprocessor, S. Lucci, Iz. Gertner, A. Gupta, and U. Hegde
€ Pentium MPP for OLTP Applications, M. Natale, M. Baker, R. Collins, D. Wilson, S. Lucci,
and Iz. Gertner
ARC 2 Reflective Memory and Distributed Shared Memory Architectures for OLTP II
€ Fault-Tolerant Disk Storage and File Systems Using Reflective Memory, N. Vekiarides
* Application-Transparent Checkpointing in Mach 3.0/UX, M. Russinovich and Z. Segall
€ MPP UNIX Enhancements for OLTP Applications, G. Schaffer
ARC 3 Reflective Memory and Distributed Shared Memory Architectures for OLTP III
€ A Distributed Lock Manager on Fault-Tolerant MPP, M. Aldred, Il. Gertner, and S. McKellar
€ Tuning Oracle7 for nCUBE, G. Arnaiz
€ A Simulation-Based Comparison of Two Reflective Memory Approaches, M. Jovanovic,
M. Tomasevic, and V. Milutinovic
HIGH PERFORMANCE COMPUTING AND I/O SYSTEMS
Coordinators: L. Ridgway Scott and Trevor Mudge
ARC 4 High Performance Computing and I/O Systems I
€ Introduction to the Minitrack, T. Mudge
€ Performance Tuning of a Multiprocessor Sparse Matrix Equation Solver, K.Y. Wu, P.K.H. Ng,
X.D. Jia, R.M.M. Chen, and A.M. Layfield
€ Architectural Synthesis with Possibilistic Programming, I. Karkowski
€ Symbolic Incompletely Specified Functions for Correct Evaluation in the Presence of
Indeterminate Input Values, G. Jennings
ARC 5 High Performance Computing and I/O Systems II
€ An Implementation of Hash Based ATM Router Chip, D. Raskovic, E. Jovanov,A.Janicijevic, and
V. Milutinovic
€ Optimized Mapping of Video Applications to Hardware-Software for VLSI Architectures,
C.H. Gebotys and R.J. Gebotys
€ Performance Analysis of Raid-5 Disk Arrays, O.A. Panfilov
€ Correlation of the Paging Activity of Individual Node Programs in the SPMD Execution
Mode, K.Y. Wang and D.C. Marinescu
ARC 6 Future Research Directions of Instruction-Level Parallel processing
Session Chairmen: Wen-mei Hwu and Scott Mahlke
The focus of the task force is to identify major research challenges and opportunities in Instruction Level Parallel Processing. As the computer companies worldwide pursue new microprocessors and systems based on Instruction Level Parallel Processing, it will become increasingly important for research organizations to produce relevant results to industry.
The end product of the task force is a document on major research challenges and opportunities in the area of instruction level parallel processing. This document will be delivered to major funding agencies, industry corporations, and universities to promote the awareness of the research area.
ARC 7 Task Force continues
INSTRUCTION LEVEL PARALLELISM
Coordinator: Robert Yung
ARC 8 Architectures and Hardware
€ Introduction to the Minitrack, R. Yung
€ An Architecture for High Instruction Level Parallelism, S. Arya, H. Sachs, and S. Duvvuru
€ The Architecture of an Optimistic CPU: The WarpEngine, J.G. Cleary, M. Pearson, and H. Kinawi
€ Evaluation of a Branch Target Address Cache, S. Duvvuru and S. Arya
ARC 9 Hardware Supports
€ An Improved Dynamic Register Array Concept for High-Performance RISC Processors, T. Scholz
and M. Schafers
€ A Three Dimensional Register File for Superscalar Processors, M. Tremblay, B. Joy, and K. Shin
€ Reducing Memory Latency Using a Small Software Driven Array Cache, C-H. Chi, C-S. Ho, and
S-C. Lau
ARC 10 Software Supports
* A Study of the Effects of Compiler-Controlled Speculation on Instruction and Data Caches,
R.A. Bringmann, S.A. Mahlke, and W-M.W. Hwu
€ Commercializing Profile-Driven Optimization, J.S. Cox, D.P. Howell, and T.M. Conte
€ A Comparative Evaluation of Software Techniques to Hide Memory Latency, L.K. John, V. Reddy,
P.T. Hulina, and L.D. Coraor
SCALABLE SHARED-MEMORY ARCHITECTURES
Coordinator: Josep Torrellas
ARC 11 Scalable Shared-Memory Architectures I
€ Introduction to the Minitrack, J. Torrellas
* Using Hints to Reduce the Read Miss Penalty for Flat COMA Protocols, M. Bjorkman,
F. Dahlgren, and P. Stenstrom
€ Decoupled Pre-Fetching for Distributed Shared Memory, I. Watson and A. Rawsthorne
€ Modeling Load Imbalance and Fuzzy Barriers for Scalable Shared-Memory Multiproces
sors, A.E. Eichenberger and S.G. Abraham
ARC 12 Scalable Shared-Memory Architectures II
€ A Survey of Software Solutions for Maintenance of Cache Consistency in Shared
Memory Multiprocessors, I. Tartalja and V. Milutinovic
€ Open Forum
LOW ENERGY ILP PROCESSORS
Coordinator: Michael A. Schuette
ARC 13 Low Energy ILP Processors I
€ Introduction to the Minitrack, M. Schuette
€ Energy Efficient CMOS Microprocessor Design, T.D. Burd and R.W. Brodersen
€ Energy-Efficient Instruction Set Architecture for CMOS Microprocessors , J. Bunda,
D. Fussell, and W.C. Athas
€ Cache Designs for Energy Efficiency, C-L. Su and A.M. Despain
ARC 14 Low Energy ILP Processors I
€ Power-Efficient Delay-Insensitive Codes for Data Transmission, P. Patra and
D.S. Fussell
* A Technique to Determine Power-Efficient, High-Performance Superscalar Processors,
T.M. Conte, K.N.P. Menezes, and S.W. Sathaye
HICSS-28 HOMEPAGE
HICSS HOMEPAGE
